The specification relates generally to an information processor and more particularly to an instruction processor.
A branch prediction mechanism of an information processor predicts a branch destination in the case of executing a branch instruction next by managing an execution history of the branch instructions on the basis of storage addresses (which will hereinafter be termed instruction addresses) in a memory of the instructions executed in the past.
In this case, the branch prediction mechanism determines a set of a storage device in a set associative system from a bit field of a portion of the instruction address (a branch source address) of the branch instruction acquired (which means that the branch instruction is fetched) from a storage source in the past. Then, the branch prediction mechanism stores a branch destination address in one way within the set by tagging still another bit field of the branch source address.
Then, the branch prediction mechanism searches the storage device by using the instruction address at an instruction fetch stage. Then, if the branch destination address of the branch instruction that was already executed in the past is stored in the storage device, the branch prediction mechanism can obtain the branch destination address from the way showing coincidence with a content of the tag within the relevant set. Namely, the branch prediction mechanism can determine in parallel with the instruction fetch whether the instruction is the branch instruction or not (whether or not the branch destination address is stored by tagging a portion of the instruction address of the branch source).
Namely, this technique enables the information processor, in parallel with the instruction fetch, to determine whether the instruction is the branch instruction or not by acquiring an address of a now-being-fetched instruction and to obtain the branch destination address predicted if the instruction is the branch instruction. Accordingly, the information processor can, even when performing a pipeline process, prepare the instruction fetch at a next stage from the branch destination predicted beforehand in parallel with the present instruction fetch.
Then, if the branch destination obtained from the now-being-fetched instruction is the predicted branch destination, the parallel operations at the respective stages can be conducted without stopping the pipeline process. Whereas if the branch destination obtained from the now-being-fetched instruction is not the predicted branch destination, it follows that the instruction fetch from a correct branch destination resumes. If the branch destination is not stored in the storage means in the manner of being associated with the instruction address of the now-being-fetched branch instruction (if the branch instruction is executed though the branch prediction is not hit) also, the branch prediction can not be utilized, and it follows that there resumes the instruction fetch from the branch destination address acquired by decoding the post-fetching branch instruction.
By the way, in the information processor, a space stored with the instruction has hitherto been a 32-bits address space. However, some information processors exist, in which the address space is extended to 64 bits corresponding to an increase in size of data to be processed. In this type of information processors, an instruction space as well as the data space is organized into 64 bits.
A size of an actual program is much smaller than 4 GB (even the largest program is on the order of several hundreds of megabits (MB)), and all the complete address for 64 bits is stored in or processed by a speculative execution processing unit, which is said to be futile in terms of hardware resources.
It is therefore efficient to organize only an inevitable portion into 64 bits, which is defined in an instruction set architecture. Such being the case, a control unit for controlling an instruction fetch speculatively based on the branch prediction uses a low-order 32-bits address to the greatest possible degree and thus controls the same instruction fetch etc as those conventional.
A specific method is that the high-order 32-bits address is fixed beforehand, and the instruction is fetched by using the fixed high-order 32-bits and a 4G bytes space of the low-order 32-bits. Then, a thinkable scheme is that if over the 4G bytes space, the high-order 32-bits are redefined.
To be specific, the high-order 32-bits of the program counter are normally fixed. Then, when there occurs such an event as to change the high-order 32-bits of the program counter by the branch instruction, exception and interruption which vary the high-order 32-bits, the high-order 32-bits are again obtained. In this case, with completion of the instruction (event) that changes the high-order 32-bits, an instruction fetch/instruction execution pipeline undergoing a speculative process is once completely cleared.
Therefore, after rewriting the high-order 32-bits of the program counter into a new value, the instruction fetch resumes with this new address. Namely, there is the event that changes the high-order 32-bits, a privilege of the speculative execution can not be received at all. Even in such a case, there must be no problem as far as the program size is small. An actual OS, however, performs control of utilizing plural sets of high-order 32-bits of the 64-bits instruction address even when the program size to be allocated is small.
In this case, a possibility that the programs disperse in the 64-bits virtual memory space is not denied. If so, even when the individual program is small, the branches over the 32-bits based 4G bytes address might frequently occur due to the branch instructions.